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| CoreAI Product Summary Intended Use * * Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an Actel Fusion Device Synthesis and Simulation Support * * * Directly Supported within Actel Libero IDE and CoreConsole Synthesis: Synplicity(R), Synopsys(R) (Design Compiler / FPGA Compiler / FPGA Express), Exemplar Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Core Verification * * Comprehensive VHDL and Verilog Testbenches User Can Easily Modify User Testbench Using Existing Format to Add Custom Tests Key Features * * * * * * ADC Conversions Controlled by MCU/MPU Writes AMBA APB Slave Interface (8- or 16-Bit Data Widths Supported) 14 Maskable Interrupt Sources Internal Clock Divider for Generating Analog Configuration MUX Clock Optional Read FIFO Stores up to 256 ADC Conversion Results Analog Configuration MUX Can Be Configured by SmartGen Contents General Description ................................................... 1 Functional Block Descriptions ................................... 3 CoreAI Device Requirements ..................................... 3 CoreAI Verification ..................................................... 3 I/O Signal Descriptions ............................................... 4 Parameter/Generic Descriptions ................................ 6 Internal CoreAI Registers ......................................... 10 ACM Interface .......................................................... 18 RTC Operation .......................................................... 21 ADC Operation ......................................................... 22 Interrupt Logic ......................................................... 23 Ordering Information .............................................. 24 Datasheet Categories ............................................... 24 Supported Families * Fusion (including M7 devices) Core Deliverables * Evaluation Version - Compiled RTL Simulation Model Fully Supported in Actel Libero(R) Integrated Design Environment (IDE) Structural Verilog and VHDL Netlists (with and without I/O Pads) Compatible with Actel Designer Software Place-and-Route Tool Compiled RTL Simulation Supported in Actel Libero IDE Model Fully * Netlist Version - General Description CoreAI (Analog Interface) allows for simple control of the analog peripherals within the Fusion family of Actel devices. Control may be implemented with an internal or external microprocessor or microcontroller (such as Core8051 or CoreMP7), or with user-created custom logic within the FPGA fabric. The industry-standard AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) slave interface is used as the primary control mechanism within CoreAI. CoreAI instantiates the AB (Analog Block) macro, as shown in Figure 1 on page 2. The AB macro includes the - * RTL Version - - Verilog and VHDL Core Source Code Core Synthesis Scripts * Testbench (Verilog and VHDL) March 2006 (c) 2006 Actel Corporation v 2 .0 1 CoreAI ACM (Analog Configuration MUX) interface, Analog Quads, and RTC (Real-Time Counter). The ACM interface, within the AB macro, is used to control configuration of the Analog Quads and RTC in the Fusion device. CoreAI generates the control signals used by the ACM, including its clock signal, which is generated by an internal clock divider. The ACM clock divider is used to ensure that the ACM interface is clocked at a frequency less than or equal to 10 MHz (refer to "ACM Interface" on page 18 for details). For more details on the silicon features of the AB macro, such as the Analog Quads, RTC, or ACM, refer to the Fusion datasheet. Several aspects of CoreAI can be configured using toplevel parameters (Verilog) or generics (VHDL). For a detailed description of the parameters/generics, refer to Table 4 on page 6. The CoreAI block diagram is shown in Figure 1. A typical application using CoreAI is shown in Figure 2. CoreAI APB I/F Interrupt Processor I/F Logic ACM I/F Logic ADC I/F Logic Analog Inputs Analog Outputs RTC Inputs RTC Outputs AB (Analog Block) Analog Inputs Used as Digital Inputs Figure 1 * CoreAI Block Diagram Fusion Device CoreMP7 CoreAI Temperature Monitor Bipolar Transistor CorePWM Figure 2 * CoreAI Typical Application 2 v2.0 CoreAI Functional Block Descriptions CoreAI, shown in Figure 1 on page 2, consists of the microprocessor interface logic, ACM interface logic, and ADC interface logic blocks. The microprocessor interface logic implements APB slave logic and generates a maskable interrupt. The ACM interface block writes configuration data into the AB macro to control Analog Quad and RTC settings. The ADC interface block sends control data to and receives status information from the ADC. CoreAI Device Requirements CoreAI has been implemented in the Actel Fusion device family. A summary of the data for CoreAI is listed in Table 1 and Table 2. Table 1 * CoreAI Device Utilization and Performance (minimum configuration) Cells or Tiles Family Fusion Sequential 45 Combinatorial 105 Total 150 Utilization Device AFS090 Total 7% Performance 150 MHz Note: Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics that differ from the default values were set as follows: FIXED_VAREFSEL = 1, FIXED_VAREFSEL_VAL = 0, FIXED_MODE = 1, FIXED_MODE_VAL = 0, FIXED_TVC = 1, FIXED_TVC_VAL = 0, FIXED_STC = 1, FIXED_STC_VAL = 0, CFG_ACx = 512, CFG_ATx = 512, DISABLE_TMSTBINT = 1, CFG_GDx = 768, ACTLOW_INTERRUPT = 0, DISABLE_INTERRUPT = 1, APB_16BIT_DATA = 1. Table 2 * CoreAI Device Utilization and Performance (maximum configuration) Family Sequential Fusion 130 Cells or Tiles Combinatorial 330 Total 460 FIFO 1 Utilization Device AFS090 Total 20% 133 MHz Performance Note: Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics that differ from the default values were set as follows: ACM_CLK_DIV = 4, USE_RTC = 1, USE_RDFIFO = 1, USE_RDFIFO_AEVAL = 16, USE_RDFIFO_AFVAL = 240. CoreAI Verification The comprehensive simulation testbench verifies correct operation of the CoreAI macro. The testbench applies several tests to the CoreAI macro, including the following: * * * Voltage monitor, current monitor, and temperature monitor tests RTC tests Gate-driver control tests Using the supplied testbench as a guide, the user can alter the verification of the core by adding custom tests or removing existing tests. v2.0 3 CoreAI I/O Signal Descriptions The port signals for the CoreAI macro are defined in Table 3 and illustrated in Figure 3. CoreAI has 120 I/O signals. Note that vector notation is used in Figure 3 for the AV, AC, AT, ATRETURN, DDGDON, DAVOUT, DACOUT, DATOUT, AG, and RTCXTLMODE ports; however, these ports are actually split into individual single-bit ports, as described in Table 3. For example, there are two individual output ports, RTCXTLMODE1 and RTCXTLMODE0, rather than one vectored output port RTCXTLMODE[1:0]. PCLK PRESETN PADDR[4:0] PSEL PENABLE PWRITE PWDATA[7:0] VAREF GNDREF AV[9:0] AC[9:0] AT[9:0] ATRETURN[4:0] DDGDON[9:0] RTCCLK PRDATA[7:0] INTERRUPT DAVOUT[9:0] DACOUT[9:0] DATOUT[9:0] AG[9:0] RTCXTLMODE[1:0] RTCXTLSEL RTCMATCH RTCPSMMATCH Figure 3 * CoreAI I/O Signal Diagram Table 3 * CoreAI I/O Signal Descriptions Name APB Interface PCLK PRESETN PADDR[4:0] PSEL PENABLE PWRITE PWDATA[15:0] Input Input Input Input Input Input Input APB System Clock: reference clock for all internal logic APB active-low asynchronous reset APB address bus - This port is used to address internal CoreAI registers. APB Slave Select - This signal selects CoreAI for reads or writes. APB Strobe - This signal indicates the second cycle of an APB transfer. APB Write/Read - If high, a write will occur when an APB transfer to CoreAI takes place; if low, a read from CoreAI will take place. APB write data - If the APB_16BIT_DATA parameter/generic is set to 1, all 16 bits are used; if the APB_16BIT_DATA parameter/generic is set to 0, only the lower 8 bits, PWDATA[7:0], are used (in this case, PWDATA[15:8] should be tied to static high or low values). APB read data - If the APB_16BIT_DATA parameter/generic is set to 1, all 16 bits are used; if the APB_16BIT_DATA parameter/generic is set to 0, only the lower 8 bits, PRDATA[7:0], are used (in this case, PRDATA[15:8] can be left unconnected). Microprocessor interrupt output - This interrupt signal is generated from 14 possible interrupt sources, each of which can be masked or enabled via the INTENABLE register. The polarity of this output is controlled via the ACTLOW_INTERRUPT parameter/generic. Type Description PRDATA[15:0] Output INTERRUPT Output Note: All signals active high (logic 1) unless otherwise noted. 4 v2.0 CoreAI Table 3 * CoreAI I/O Signal Descriptions (Continued) Name Analog Interface VAREF Input or Output Input Input Voltage reference - If using the internal voltage reference, this signal will be an output; if using an external voltage reference, this signal will be an input for this reference (see the FIXED_VAREFSEL and FIXED_VAREFSEL_VAL parameters/generics). Ground reference - If external voltage reference is used, this signal must be connected to the ground for the reference; otherwise this should be connected to digital ground (logic 0). Analog Voltage Monitor inputs - These signals correspond to the AVx voltage monitor inputs (AV9 through AV0) of the AB macro. Note: Unused AVx inputs need to be disabled with the CFG_AVx parameters/generics and connected to logic 0. AC9, AC8, AC7, AC6, AC5, AC4, AC3, AC2, AC1, AC0 Input Analog Current Monitor inputs - These signals correspond to the ACx current monitor inputs (AC9 through AC0) of the AB macro. Note: Unused ACx inputs need to be disabled with the CFG_ACx parameters/generics and connected to logic 0. AT9, AT8, AT7, AT6, AT5, AT4, AT3, AT2, AT1, AT0 Input Analog Temperature Monitor inputs - These signals correspond to the ATx temperature monitor inputs (AT9 through AT0) of the AB macro. Note: Unused ATx inputs need to be disabled with the CFG_ATx parameters/generics and connected to logic 0. ATRETURN4, ATRETURN3, ATRETURN2, ATRETURN1, ATRETURN0] DAVOUT9, DAVOUT8, DAVOUT7, DAVOUT6, DAVOUT5, DAVOUT4, DAVOUT3, DAVOUT2, DAVOUT1, DAVOUT0 DACOUT9, DACOUT8, DACOUT7, DACOUT6, DACOUT5, DACOUT4, DACOUT3, DACOUT2, DACOUT1, DACOUT0 DATOUT9, DATOUT8, DATOUT7, DATOUT6, DATOUT5, DATOUT4, DATOUT3, DATOUT2, DATOUT1, DATOUT0 DDGDON9, DDGDON8, DDGDON7, DDGDON6, DDGDON5, DDGDON4, DDGDON3, DDGDON2, DDGDON1, DDGDON0 AG9, AG8, AG7 AG6, AG5, AG4, AG3, AG2, AG1, AG0 Input Shared Analog Temperature Monitor Returns - These signals correspond to the shared returns for the temperature monitor inputs (ATRETURN89 through ATRETURN01) of the AB macro. Digital AV outputs - These signals correspond to the digital AV outputs (DAVOUT9 through DAVOUT0) of the AB macro. If any of the AVx inputs are configured as digital inputs rather than analog inputs, their corresponding buffered digital signals are put out on these ports. Type Description GNDREF AV9, AV8, AV7, AV6, AV5, AV4, AV3, AV2, AV1, AV0 Output Output Digital AC outputs - These signals correspond to the digital AC outputs (DACOUT9 through DACOUT0) of the AB macro. If any of the ACx inputs are configured as digital inputs rather than analog inputs, their corresponding buffered digital signals are put out on these ports. Output Digital AT outputs - These signals correspond to the digital AT outputs (DATOUT9 through DATOUT0) of the AB macro. If any of the ATx inputs are configured as digital inputs rather than analog inputs, their corresponding buffered digital signals are put out on these ports. Input Direct Digital Gate Driver enables - These signals can control the corresponding GDONx gate-driver enable inputs (GDON9 through GDON0) of the AB macro if the CFG_GDx parameters/generics are set appropriately (refer to "Parameter/Generic Descriptions" on page 6). Analog Gate Driver outputs - These signals correspond to the AGx gate driver outputs (AG9 through AG0) of the AB macro. Note: If unused, each of these gate driver outputs can be disabled via the CFG_GDx parameters/generics. Output Note: All signals active high (logic 1) unless otherwise noted. v2.0 5 CoreAI Table 3 * CoreAI I/O Signal Descriptions (Continued) Name RTCCLK Type Input Description RTC Clock input - If the RTC is used (via the USE_RTC parameter/generic), this input must come from the internal crystal oscillator (XTLOSC) CLKOUT pin; if the RTC is not used, this pin should be tied low. RTC XTLOSC Mode outputs - If the RTC is used (via the USE_RTC parameter/generic), these output ports must be connected to the internal crystal oscillator (XTLOSC) RTCMODE[1:0] pins; if the RTC is not used, these pins should be left unconnected. RTC XTLOSC Mode Selection output - If the RTC is used (via the USE_RTC parameter/ generic), this output port must be connected to the internal crystal oscillator (XTLOSC) MODESEL pin; if the RTC is not used, this pin should be left unconnected. RTC Match output - If the RTC is used (via the USE_RTC parameter/generic), this output port indicates that a match event has occurred and can be connected to other FPGA logic; if the RTC is not used, this pin should be left unconnected. RTC Match VRPSM output - If the RTC is used (via the USE_RTC parameter/generic), this output port can be connected to the VRPSM pin of the internal voltage regulator to control regulator power-up; if the RTC is not used, this pin should be left unconnected. RTCXTLMODE1, RTCXTLMODE0 RTCXTLSEL Output Output RTCMATCH Output RTCPSMMATCH Output Note: All signals active high (logic 1) unless otherwise noted. Parameter/Generic Descriptions CoreAI has parameters (Verilog) and generics (VHDL), described in Table 4, for configuring the RTL code. All parameters and generics are integer types. Table 4 * CoreAI Parameters/Generics Descriptions Name APB_16BIT_DATA Valid Range 0 or 1 Description Set this to 1 if the APB reads and writes are using all 16-bits of the PRDATA[15:0] and PWDATA[15:0] ports, or to 0 if 8-bit APB reads and writes are done on the PRDATA[15:0] and PWDATA[15:0] ports. If 8-bit APB reads and writes are used, only the lower eight bits of each port are used, i.e., PRDATA[7:0] and PWDATA[7:0]; PWDATA[15:8] should be tied statically high or low and PRDATA[15:8] should be left unconnected in this case. Note that for 16-bit reads and writes, the internal address map shown in Table 9 on page 11 will concatenate adjacent bytes since PADDR[0] will be ignored; in this case, each byte that is addressed by PADDR[0] = 0 will correspond to the LSB and each byte that is addressed by PADDR[0] = 1 will correspond to the MSB of each 16-bit word. The default value of 0 uses 8-bit APB reads and writes. Interrupt Active Low: Set this to 1 if the INTERRUPT output polarity is active low, or to 0 if the INTERRUPT output polarity is active high. The default value of 0 is active high. Disable Interrupt: Set this to 1 if the INTERRUPT output will not be used, in which case the INTERRUPT output will be fixed at the inactive polarity chosen by ACTLOW_INTERRUPT, i.e., INTERRUPT = ACTLOW_INTERRUPT; set this to 0 if the INTERRUPT output is used. The default value of 0 uses the INTERRUPT output. ACTLOW_INTERRUPT 0 or 1 DISABLE_INTERRUPT 0 or 1 Note: *Invalid values are 3, 7, 11, and 15 (refer to the Fusion datasheet). 6 v2.0 CoreAI Table 4 * CoreAI Parameters/Generics Descriptions (Continued) Name ACM_CLK_DIV Valid Range 1 to 4 Description Set this to the division value to generate the ACM clock, which has a maximum frequency of 10 MHz. The actual value will be the frequency of PCLK divided by (2ACM_CLK_DIV); valid values are 1-4. The default value of 1 sets the ACM clock at half the PCLK frequency. Note: It is the user's responsibility to ensure that the ACM clock has a maximum operating frequency of 10 MHz. USE_RTC USE_RDFIFO 0 or 1 0 or 1 Use RTC: Set this to 1 if the RTC is to be used, or to 0 if the RTC is not to be used. The default value of 0 does not use the RTC. Use Read FIFO: Set this to 1 if using an internal data FIFO for storing up to 256 ADC conversion results for later reading by a microprocessor, or to 0 if not using the FIFO. The default value of 0 does not use a read FIFO. Read FIFO Almost Empty Value: Set this 8-bit integer to the fixed almost empty value of the read FIFO. This value determines when the almost empty flag output from the read FIFO becomes active; it represents the number of 16-bit ADC conversion result words that are left to be read before the read FIFO will be empty. Note: This is only used if USE_RDFIFO = 1. USE_RDFIFO_AFVAL 0 to 255 Read FIFO Almost Full Value: Set this 8-bit integer to the fixed almost full value of the read FIFO. This value determines when the almost full flag output from the read FIFO becomes active; it represents the number of 16-bit ADC conversion result words that are left to be written before the read FIFO will be full. Note: This is only used if USE_RDFIFO = 1. FIXED_VAREFSEL 0 or 1 Set this to 1 if the VAREFSEL input pin of the AB macro is to be fixed, or to 0 to allow register-controlled VAREFSEL setting (saves some logic tiles for a fixed system). The default value of 0 does not have a fixed VAREFSEL setting. Fixed VAREFSEL Value: Set this to a 1-bit constant value (set in higher-level wrapper). Set to 1 to select external VAREF as input, 0 to select internal VAREF as output. Note: This is only used if FIXED_VAREFSEL = 1. FIXED_MODE 0 or 1 Set this to 1 if the MODE[3:0] pins of the AB macro are a fixed constant, or to 0 to allow register-controlled MODE[3:0] setting (saves some logic tiles for a fixed system). The default of 0 does not have a fixed MODE[3:0] setting. Fixed MODE Value: Set this to the integer value of the 4-bit fixed constant connected to the MODE[3:0] input pins of the AB macro (controls ADC resolution, etc.). Note: This is only used if FIXED_MODE = 1. Set this to 1 if the TVC[7:0] pins of the AB macro are a fixed constant, or to 0 to allow register-controlled TVC[7:0] setting (saves some logic tiles for a fixed system). The default value of 0 does not have a fixed TVC[7:0] setting. Fixed TVC Value: Set this to the integer value of the 8-bit fixed constant connected to the TVC[7:0] inputs of the AB macro. Note: This is only used if FIXED_TVC = 1. FIXED_STC 0 or 1 Set this to 1 if the STC[7:0] pins of the AB macro are a fixed constant, or to 0 to allow register-controlled STC[7:0] setting (saves some logic tiles for a fixed system). The default value of 0 does not have a fixed STC[7:0] setting. USE_RDFIFO_AEVAL 0 to 255 FIXED_VAREFSEL_VAL 0 or 1 FIXED_MODE_VAL 0 to 2, 4 to 6, 8 to 10, 12 to 14* 0 or 1 FIXED_TVC FIXED_TVC_VAL 0 to 255 Note: *Invalid values are 3, 7, 11, and 15 (refer to the Fusion datasheet). v2.0 7 CoreAI Table 4 * CoreAI Parameters/Generics Descriptions (Continued) Name FIXED_STC_VAL Valid Range 0 to 255 Description Fixed STC Value: Set this to the integer value of the 8-bit fixed constant connected to the STC[7:0] inputs of the AB macro. Note: This is only used if FIXED_STC = 1. DISABLE_TMSTBINT 0 or 1 Disable Internal Temperature Monitor Strobe: Set this 1-bit integer to disable the internal temperature monitor strobes. If this bit is set to 1, the TMSTBINT input is disabled; if it is set to 0, the TMSTBINT input is register-controlled. The default value of 0 allows the internal temperature monitor strobe to be controlled via register settings. Configure AVx Inputs: Set each of these 10-bit integers to configure the AV9 through AV0 inputs that are connected to the AB macro. The lower 8 bits of each of these 10-bit integers are reserved for generating firmware settings for the target processor used with CoreAI and are ignored by the CoreAI hardware. The upper 2 bits are used to create the settings for each AVx input, shown in Table 5 on page 9. For example, if CFG_AV5 is set to the binary value 0000000000 (decimal 0), the AV5 input will be used as an analog voltage monitor input. If CFG_AV5 is set to the binary value 0100000000 (decimal 256), the AV5 input will be used as a digital input, and the buffered DAVOUT5 output would be connected to the user's own logic. If CFG_AV5 is set to the binary value 1100000000 (decimal 768), the AV5 input will be disabled; in this case, the CoreAI AV5 input will not be used and the AV5 input of the AB macro will be hardwired to logic 0 within CoreAI. Configure ACx Inputs: Set each of these 10-bit integers to configure the AC9 through AC0 inputs that are connected to the AB macro. The lower 8 bits of each of these 10-bit integers are reserved for generating firmware settings for the target processor used with CoreAI and are ignored by the CoreAI hardware. The upper 2 bits are used to create the settings for each ACx input, shown in Table 6 on page 9. For example, if CFG_AC7 is set to the binary value 0000000000 (decimal 0), the AC7 input will be used as an analog current monitor input. If CFG_AC7 is set to the binary value 0100000000 (decimal 256), the AC7 input will be used as a digital input, and the buffered DACOUT7 output would be connected to the user's own logic. If CFG_AC7 is set to the binary value 1000000000 (decimal 512), the AC7 input will be used as an analog voltage monitor input. If CFG_AC7 is set to the binary value 1100000000 (decimal 768), the AC7 input will be disabled; in this case, the CoreAI AC7 input will not be used and the AC7 input of the AB macro will be hardwired to logic 0 within CoreAI. CFG_AV9, CFG_AV8, CFG_AV7, CFG_AV6, CFG_AV5, CFG_AV4, CFG_AV3, CFG_AV2, CFG_AV1, CFG_AV0 0 to 1,023 CFG_AC9, CFG_AC8, CFG_AC7, CFG_AC6, CFG_AC5, CFG_AC4, CFG_AC3, CFG_AC2, CFG_AC1, CFG_AC0 0 to 1,023 Note: *Invalid values are 3, 7, 11, and 15 (refer to the Fusion datasheet). 8 v2.0 CoreAI Table 4 * CoreAI Parameters/Generics Descriptions (Continued) Name CFG_AT9, CFG_AT8, CFG_AT7, CFG_AT6, CFG_AT5, CFG_AT4, CFG_AT3, CFG_AT2, CFG_AT1, CFG_AT0 Valid Range 0 to 1,023 Description Configure ATx Inputs: Set each of these 10-bit integers to configure the AT9 through AT0 inputs that are connected to the AB macro. The lower 8 bits of each of these 10-bit integers are reserved for generating firmware settings for the target processor used with CoreAI and are ignored by the CoreAI hardware. The upper 2 bits are used to create the settings for each ATx input, shown in Table 7 on page 10. For example, if CFG_AT2 is set to the binary value 0000000000 (decimal 0), the AT2 input will be used as an analog temperature monitor input. If CFG_AT2 is set to the binary value 0100000000 (decimal 256), the AT2 input will be used as a digital input, and the buffered DATOUT2 output would be connected to the user's own logic. If CFG_AT2 is set to the binary value 1000000000 (decimal 512), the AT2 input will be used as an analog voltage monitor input. If CFG_AT2 is set to the binary value 1100000000 (decimal 768), the AT2 input will be disabled; in this case, the CoreAI AT2 input will not be used and the AT2 input of the AB macro will be hardwired to logic 0 within CoreAI. Configure Gate Drivers: Set each of these 10-bit integers to configure the GDON9 through GDON0 inputs and the AG9 through AG0 outputs that are connected to the AB macro. The lower 8 bits of each of these 10-bit integers are reserved for generating firmware settings for the target processor used with CoreAI and are ignored by the CoreAI hardware. The upper 2 bits are used to create the settings shown in Table 8 on page 10. For example, if CFG_GD1 is set to the binary value 0000000000 (decimal 0), the AG1 gate-driver output will be controlled by a software-controlled register within CoreAI (ADC Control Register 5). If CFG_GD1 is set to the binary value 0100000000 (decimal 256), the DDGDON1 input (connected to the user's own logic) will be used to directly control the AG1 gate-driver output. If CFG_GD1 is set to the binary value 1100000000 (decimal 768), the AG1 output will be disabled; in this case, the CoreAI AG1 output will not be used and the GDON1 input of the AB macro will be hardwired to logic 0 within CoreAI. CFG_GD9, CFG_GD8, CFG_GD7, CFG_GD6, CFG_GD5, CFG_GD4, CFG_GD3, CFG_GD2, CFG_GD1, CFG_GD0 0 to 1,023 Note: *Invalid values are 3, 7, 11, and 15 (refer to the Fusion datasheet). Table 5 * Settings for AVx Inputs CFG_AVx Bit-Position Values ('X' indicates "don't care") 9 0 0 1 1 8 0 1 0 1 7 X X X X 6 X X X X 5 X X X X 4 X X X X 3 X X X X 2 X X X X 1 X X X X 0 X X X X AVx Input Usage Voltage Monitor (default) Digital Input Reserved (unused) Disabled Table 6 * Settings for ACx Inputs CFG_ACx Bit-Position Values ('X' indicates "don't care") 9 0 0 1 1 8 0 1 0 1 7 X X X X 6 X X X X 5 X X X X 4 X X X X 3 X X X X 2 X X X X 1 X X X X 0 X X X X ACx Input Usage Current Monitor (default) Digital Input Voltage Monitor Disabled v2.0 9 CoreAI Table 7 * Settings for ATx Inputs CFG_ATx Bit-Position Values ('X' indicates "don't care") 9 0 0 1 1 8 0 1 0 1 7 X X X X 6 X X X X 5 X X X X 4 X X X X 3 X X X X 2 X X X X 1 X X X X 0 X X X X ATx Input Usage Temperature Monitor (default) Digital Input Voltage Monitor Disabled Table 8 * Settings for Gate Driver Usage CFG_GDx Bit-Position Values ('X' indicates "don't care") 9 0 1 1 1 8 0 0 0 1 7 X X X X 6 X X X X 5 X X X X 4 X X X X 3 X X X X 2 X X X X 1 X X X X 0 X X X X Gate Driver Usage Register controlled (default) Gate Driver (AGx) DDGDONx input Reserved (unused) Disabled (GDONx and AGx) controlled by Internal CoreAI Registers The internal register address map and reset values of each APB-accessible register for CoreAI are shown in Table 9 on page 11. In the case of 8-bit APB reads and writes (APB_16BIT_DATA = 0), each PADDR[4:0] address is significant and contains the byte listed in the far right column; however, when 16-bit APB reads and writes are used (APB_16BIT_DATA = 1), PADDR[4:1] addresses contain one 16-bit word, where each two adjacent rows in Table 9 on page 11 contain the low-order and highorder bytes, consecutively (PADDR[0] is unused in this case). Table 10 on page 12 through Table 31 on page 17 describe the various APB-accessible registers within CoreAI. Unless otherwise stated, each register can be read from or written to by an internal or external microprocessor/microcontroller. All registers are listed assuming 8-bit APB reads and writes; if 16-bit APB reads and writes are used, add 8 to each item in the "Bits" column for high-order bytes (Table 11 on page 12, Table 15 on page 13, Table 17 on page 13, Table 19 on page 14, Table 21 on page 14, Table 23 on page 14, Table 25 on page 15, Table 29 on page 16, and Table 31 on page 17). When reading from register bits that are write-only or unused (reserved), a logic 0 will be returned. When writing to register bits that are read-only or unused (reserved), no action takes place. The INTERRUPT output is generated as the logical OR of the interrupt enable bits (INTEN[14:0]) ANDed with the interrupt status bits (INT[14:0]), as shown in Figure 4. INTEN[14] INT[14] INTERRUPT INTEN[0] INT[0] Figure 4 * CoreAI Interrupt Logic 10 v2.0 CoreAI Note that after an APB read of the interrupt status registers has been performed, each INT[14:0] bit will be cleared if its condition is no longer valid. If an APB read of the interrupt status registers has just occurred coincident with a pending interrupt condition, the interrupt condition will have priority in order to prevent a missed interrupt. Table 9 * CoreAI Internal Register Address Map* PADDR[4:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Type R/W R/W R/W - R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R - R - R/W R/W R R Reset Value 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x00 0x00 Brief Description ACM Control/Status Register (low-order) ACM Control/Status Register (high-order) ACM Address Register Reserved ACM Data Register Reserved ADC Control Register 1 (low-order) ADC Control Register 1 (high-order) ADC Control Register 2 (low-order) ADC Control Register 2 (high-order) ADC Control Register 3 (low-order) ADC Control Register 3 (high-order) ADC Control Register 4 (low-order) ADC Control Register 4 (high-order) ADC Control Register 5 (low-order) ADC Control Register 5 (high-order) ADC Status Register (low-order) ADC Status Register (high-order) Read FIFO Data Output Reserved Read FIFO Status Reserved Interrupt Enable Register (low-order) Interrupt Enable Register (high-order) Interrupt Status Register (low-order) Interrupt Status Register (high-order) Note: *Values shown in hexadecimal format. Type designations: "R" - read-only, "R/W" - read/write, "-" - Not used (to accommodate 16-bit APB access) v2.0 11 CoreAI Table 10 * ACM Control/Status Register (low-order) Bits 7:5 4 3 2 1 Name Reserved ACMWRBUSY ACMRDBUSY ACMRESETBUSY ACMRDSTART Not used ACM Write Cycle Busy (read-only) - If 1, the ACM is busy writing data into the AB block. ACM Read Cycle Busy (read-only) - If 1, the ACM is busy reading data from the AB block. ACM Reset Cycle Busy (read-only) - If 1, the ACM is busy being reset. ACM Read Start (write-only) 1 - The ACM starts a read cycle from the ACM address in the ACMADDR[7:0] bits of the ACM Address/Data register. Note that this write-only bit is active for one ACM clock cycle (self-clearing), and that the resulting busy signal from the ACM read taking place will be reflected in the ACMRDBUSY bit of this register. 0 - Normal (no operation or current ACM operation continues) 0 ACMRESET ACM Reset (write-only) 1 - The ACM is put into a reset condition. Note that this write-only bit is active for only one ACM clock cycle (self-clearing), and that the resulting busy signal from the ACM reset taking place will be reflected in the ACMRESETBUSY bit of this register. 0 - Normal (no operation or current ACM operation continues) Table 11 * ACM Control/Status Register (high-order) Bits 7:0 Name Reserved Not used Function Function Table 12 * ACM Address Register Bits 7:0 Name ACMADDR[7:0] ACM Address These bits are connected to the ACMADDR[7:0] port of the AB macro. (Refer to the Fusion datasheet for further information.) Table 13 * ACM Data Register Bits 7:0 Name ACMDATA[7:0] ACM Data If this register is read from, the ACMRDATA[7:0] output port from the AB block is returned. If this register is written to, it will drive the ACMWDATA[7:0] input port of the AB block. Function Function 12 v2.0 CoreAI Table 14 * ADC Control Register 1 (low-order) Bits 7 6 Name Reserved ADCRESET Not used ADC Reset (write-only) 1 - The ADC is given an active high pulse (connected to the ADCRESET pin of the AB macro). Note that this write-only bit is active for only one PCLK clock cycle (self-clearing). 0 - Normal (no operation or current conversion continues) 5 PWRDN ADC Power Down 1 - The ADC is powered down. 0 - The ADC is powered up (normal operation). 4 VAREFSEL ADC Voltage Reference Select 1 - Select external voltage reference (3.3 V max.) to be used (input on VAREF and GNDREF ports) 0 - Select internal voltage reference (2.56 V) to be used (output on VAREF port) 3:0 MODE[3:0] ADC Mode Selection The mode selection bits are used to select between 8-, 10-, and 12-bit ADC resolution. (Refer to the Fusion datasheet for further information.) Table 15 * ADC Control Register 1 (high-order) Bits 7:0 Name TVC[7:0] ADC Clock Divider (Refer to the Fusion datasheet for further information.) Table 16 * ADC Control Register 2 (low-order) Bits 7:0 Name STC[7:0] ADC Sample Time Control (Refer to the Fusion datasheet for further information.) Table 17 * ADC Control Register 2 (high-order) Bits 7:6 5 Name Reserved ADCSTART Not used ADC Start Conversion (write-only) 1 - The ADC starts an analog-to-digital conversion on the selected channel. Note that this writeonly bit is high for only one PCLK clock cycle (self-clearing). 0 - Normal (no operation or current conversion continues) 4:0 CHNUMBER[4:0] ADC Channel Number This 5-bit value selects one of 32 analog channels that are fed to the analog MUX within the AB macro. (Refer to the Fusion datasheet for further information.) Table 18 * ADC Control Register 3 (low-order) Bits 7:0 Name CMSTB[7:0] Current Monitor Strobes These bits are connected to the CMSTB[7:0] pins of the AB macro. (Refer to the Fusion datasheet for further information.) Function Function Function Function Function v2.0 13 CoreAI Table 19 * ADC Control Register 3 (high-order) Bits 7:2 1:0 Name Reserved CMSTB[9:8] Not used Current Monitor Strobes These bits are connected to the CMSTB9 and CMSTB8 pins of the AB macro. (Refer to the Fusion datasheet for further information.) Table 20 * ADC Control Register 4 (low-order) Bits 7:0 Name TMSTB[7:0] Temperature Monitor Strobes These bits are connected to the TMSTB[7:0] pins of the AB macro. (Refer to the Fusion datasheet for further information.) Table 21 * ADC Control Register 4 (high-order) Bits 7:2 2 Name Reserved TMSTBINT Not used Internal Temperature Monitor Strobe This bit is connected to the TMSTBINT pin of the AB macro. (Refer to the Fusion datasheet for further information.) 1:0 TMSTB[9:8] Temperature Monitor Strobes These bits are connected to the TMSTB9 and TMSTB8 pins of the AB macro. (Refer to the Fusion datasheet for further information.) Table 22 * ADC Control Register 5 (low-order) Bits 7:0 Name GDON[7:0] Gate Driver Enables These bits are connected to the GDON[7:0] pins of the AB macro. Note that the CFG_GDx parameters/generics settings affect whether or not the GDON[7:0] register bits are used. (Refer to the Fusion datasheet for further information.) Table 23 * ADC Control Register 5 (high-order) Bits 7:2 1:0 Name Reserved GDON[9:8] Not used Gate Driver Enables These bits are connected to the GDON9 and GDON8 pins of the AB macro. Note that the CFG_GDx parameters/generics settings affect whether or not the GDON[9:8] register bits are used. (Refer to the Fusion datasheet for further information.) Table 24 * ADC Status Register (low-order) Bits 7:0 Name RESULT[7:0] ADC Result (low-order) These bits come from the RESULT[7:0] bits of the AB macro. (Refer to the Fusion datasheet for further information.) Function Function Function Function Function Function 14 v2.0 CoreAI Table 25 * ADC Status Register (high-order) Bits 7 Name CALIBRATE ADC Calibrate 1 - The ADC is busy performing its calibration. 0 - The ADC is calibrated. (Refer to the Fusion datasheet for further information.) 6 SAMPLE ADC Sample 1 - The ADC is sampling the selected analog input. 0 - Normal (no operation or the ADC has finished the sampling phase) (Refer to the Fusion datasheet for further information.) 5 BUSY ADC Busy 1 - The ADC is busy performing an analog-to-digital conversion. 0 - The ADC is not busy. (Refer to the Fusion datasheet for further information.) 4 DATAVALID ADC Data Valid 1 - The ADC contains valid data from an analog-to-digital conversion on the RESULT[11:0] outputs. 0 - Normal (no operation or current conversion continues) (Refer to the Fusion datasheet for further information.) 3:0 RESULT[11:8] ADC Result (high-order) These bits come from the RESULT[11:8] bits of the AB macro. (Refer to the Fusion datasheet for further information.) Table 26 * Read FIFO Data Output Register Bits 7:0 Name DOUT[7:0] Read FIFO Data Output If CoreAI is used in 8-bit APB read/write mode, the read FIFO must be read twice to retrieve one ADC sample of result data (two bytes); in this case, the low-order byte would be read first and the high-order byte second. Note also that in 8-bit APB read/write mode, the read FIFO will not become empty until the last high-order byte has been read from the FIFO, i.e., an even number of reads must occur. If CoreAI is used in 16-bit APB read/write mode, the read FIFO will be read as one 16-bit word at once (with only the lower 12 bits being significant, since the ADC result has 12 bits of resolution); in this case, DOUT[15:0] will appear on the PRDATA[15:0] output port, rather than DOUT[7:0] appearing on PRDATA[7:0] as in 8-bit mode. Function Function v2.0 15 CoreAI Table 27 * Read FIFO Status Register Bits 7:4 3 Name Reserved AEMPTY Not used Read FIFO Almost Empty 1 - The read FIFO is almost empty (based on the value of the USE_RDFIFO_AEVAL parameter/ generic). 0 - The read FIFO is not almost empty. 2 EMPTY Read FIFO Empty 1 - The read FIFO is empty. 0 - The read FIFO is not empty. 1 AFULL Read FIFO Almost Full 1 - The read FIFO is almost full (based on the value of the USE_RDFIFO_AFVAL parameter/generic). 0 - The read FIFO is not almost full. 0 FULL Read FIFO Full 1 - The read FIFO is full. 0 - The read FIFO is not full. Table 28 * Interrupt Enable Register (low-order) Bits 7 6:0 Name Reserved INTEN[6:0] Not used Low-Order Interrupt Enables Each of these bits is ANDed with each of the bits in the INT[6:0] register to contribute to the ORed INTERRUPT output. To mask the contribution of the corresponding bit in the INT[6:0] register, set that bit to 0; to enable the contribution, set that bit to 1. Note that the INTEN[6:0] bits only mask what appears on the INTERRUPT output and that the INT[6:0] register bits will always be active to reflect current interrupt source conditions. Table 29 * Interrupt Enable Register (high-order) Bits 7:0 Name INTEN[14:7] High-Order Interrupt Enables Each of these bits is ANDed with each of the bits in the INT[14:7] register to contribute to the ORed INTERRUPT output. To mask the contribution of the corresponding bit in the INT[14:7] register, set that bit to 0; to enable the contribution, set that bit to 1. Note that the INTEN[14:7] bits only mask what appears on the INTERRUPT output and that the INT[14:7] register bits will always be active to reflect current interrupt source conditions. Function Function Function 16 v2.0 CoreAI Table 30 * Interrupt Status Register (low-order) Bits 7 6 5 4 3 Name Reserved INT[6] INT[5] INT[4] INT[3] Not used RTC Match Rising Edge - If 1, the RTCMATCH output has transitioned high, indicating that the RTC has reached the desired count. ACM Read Done - If 1, an ACM read cycle has completed and valid data can be read from the ACM DATA register. ACM Write Done - If 1, an ACM write cycle has completed and valid data has been written into the AB macro. DATAVALID Rising Edge - If 1, the DATAVALID signal from the AB block has transitioned high, indicating that valid converted data from the ADC is available on the RESULT[11:0] output port from the AB block. BUSY Rising Edge - If 1, the BUSY signal from the AB block has transitioned high, indicating that the ADC has begun an analog-to-digital conversion and is now busy performing that conversion. CALIBRATE Falling Edge - If 1, the CALIBRATE signal from the AB block has transitioned low, indicating that the ADC has finished its calibration procedure. CALIBRATE Rising Edge - If 1, the CALIBRATE signal from the AB block has transitioned high, indicating that the ADC has started its calibration procedure. Function 2 1 0 INT[2] INT[1] INT[0] Table 31 * Interrupt Status Register (high-order) Bits 7 6 5 4 3 2 1 0 Name INT[14] INT[13] INT[12] INT[11] INT[10] INT[9] INT[8] INT[7] Function Read FIFO Almost Empty Rising Edge - If 1, the Almost Empty flag from the read FIFO has transitioned high, indicating that it is almost empty. Read FIFO Almost Empty Falling Edge - If 1, the Almost Empty flag from the read FIFO has transitioned low, indicating that it is no longer almost empty. Read FIFO Empty Rising Edge - If 1, the Empty flag from the read FIFO has transitioned high, indicating that it is now empty. Read FIFO Empty Falling Edge - If 1, the Empty flag from the read FIFO has transitioned low, indicating that it is no longer empty. Read FIFO Almost Full Rising Edge - If 1, the Almost Full flag from the read FIFO has transitioned high, indicating that it is almost full. Read FIFO Almost Full Falling Edge - If 1, the Almost Full flag from the read FIFO has transitioned low, indicating that it is no longer almost full. Read FIFO Full Rising Edge - If 1, the Full flag from the read FIFO has transitioned high, indicating that it is now full. Read FIFO Full Falling Edge - If 1, the Full flag from the read FIFO has transitioned low, indicating that it is no longer full. v2.0 17 CoreAI ACM Interface The ACM interface is used to configure the analog quads and RTC within the AB macro. Various features of the analog quads need to be set prior to correct operation of the ADC, including the pre-scaler circuits in each of the AV, AC, and AT analog input ports that will be accessed in the user's design. The SmartGen software, included with Libero IDE, can be used to configure the various pre-scaler settings for each quad, as well as the functions used (voltage monitor, current monitor, temperature monitor, gate-driver output driver strengths, etc.). Consult the Fusion datasheet for details on how each pre-scaler should be set, relative to the design-specific voltage, current, or temperature ranges used. The internal address map of the ACM is shown in Table 32. Note that the ACM must operate with a clock frequency that is less than or equal to 10 MHz; to achieve this requirement, the user must set the clock-divider appropriately via the ACM_CLK_DIV parameter/generic. For example, if the system clock frequency (PCLK) is 50 MHz, ACM_CLK_DIV can be set to 3, which would generate an ACM clock frequency of 50/(23) = 6.25 MHz. ACM reads and writes are synchronized to the internally generated ACM clock. Since the ACM clock is operating at a lower frequency than the system clock (PCLK) used by CoreAI, various status and interrupt status registers have been implemented to indicate when ACM read and write accesses are busy or completed (see Table 10 on page 12 and Table 30 on page 17). Table 32 * ACM Address Map (Analog Quads and RTC)* PADDR[4:0] 0x00 Analog Quad 0 0x01 0x02 0x03 0x04 Analog Quad 1 0x05 0x06 0x07 0x08 ... Analog Quad 9 0x25 0x26 0x27 0x28 0x29 0x30 ... 0x3E AQ9 AQ9 AQ9 AQ9 - - ... - Byte 0 (AV9 control) Byte 2 (AC9 control) Byte 2 (AG9 control) Byte 3 (AT9 control) Reserved Reserved ... Reserved Analog Quad Analog Quad Analog Quad Analog Quad Unused Unused Unused Unused AQ1 AQ1 AQ1 AQ1 ... Byte 0 (AV1 control) Byte 1 (AC1 control) Byte 2 (AG1 control) Byte 3 (AT1 control) ... Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad AQ0 AQ0 AQ0 AQ0 Byte 0 (AV0 control) Byte 1 (AC0 control) Byte 2 (AG0 control) Byte 3 (AT0 control) Analog Quad Analog Quad Analog Quad Analog Quad Name - Description Reserved Associated Peripheral Unused Note: *Address values are given in hexadecimal format. 18 v2.0 CoreAI Table 32 * ACM Address Map (Analog Quads and RTC)* (Continued) PADDR[4:0] Real-Time Counter 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x60 0x61 ... 0xFF - COUNTER0 COUNTER1 COUNTER2 COUNTER3 COUNTER4 - - - MATCHREG0 MATCHREG1 MATCHREG2 MATCHREG3 MATCHREG4 - - - MATCHBITS0 MATCHBITS1 MATCHBITS2 MATCHBITS3 MATCHBITS4 - - - CTRL_STAT TEST_REG - - ... - Reserved Counter bits 7:0 Counter bits 15:8 Counter bits 23:16 Counter bits 31:24 Counter bits 39:32 Reserved Reserved Reserved Match register bits 7:0 Match register bits 15:8 Match register bits 23:16 Match register bits 31:24 Match register bits 39:32 Reserved Reserved Reserved Individual match bits 7:0 Individual match bits 15:8 Individual match bits 23:16 Individual match bits 31:24 Individual match bits 39:32 Reserved Reserved Reserved Control (write) / Status (read) register bits 7:0 Test register(s) Reserved Reserved ... Reserved Unused RTC RTC RTC RTC RTC Unused Unused Unused RTC RTC RTC RTC RTC Unused Unused Unused RTC RTC RTC RTC RTC Unused Unused Unused RTC RTC Unused Unused Unused Unused Name Description Associated Peripheral Note: *Address values are given in hexadecimal format. v2.0 19 CoreAI ACM Writes An example of writing data into the ACM is illustrated in Figure 5. The steps for writing information into the AB block via the ACM are as follows: 1. Read the ACM Control/Status register to make sure that CoreAI is not busy processing an ACM read or write. PCLK PADDR[4:0] PWRITE PSEL PENABLE PWDATA[7:0] PRDATA[7:0] 00 ACMADDR[7:0] ACMCtrlStat ACMAddr 2. Write the desired ACM address to the ACM Address register. 3. Write the desired ACM data to the ACM Data register. 4. Keep reading the ACM Control/Status register until CoreAI is not busy processing the ACM write. ACMData ACMCtrlStat ACMDATA[7:0] 08 00 Note: 8-bit APB reads and writes are shown. Figure 5 * ACM Write Procedure ACM Reads An example of reading data from the ACM is illustrated in Figure 6. The steps for reading information from the AB block via the ACM are as follows: 1. Read the ACM Control/Status register to make sure that CoreAI is not busy processing an ACM read or write. 2. Write the desired ACM address to the ACM Address register. 3. Write a logic 1 to the ACMRDSTART bit of the ACM Control/Status register. 4. Keep reading the ACM Control/Status register until CoreAI is not busy processing the ACM read. 5. Read the ACM Data register to read the byte of ACM data that is now available from the AB block. PCLK PADDR[4:0] PWRITE PSEL PENABLE PWDATA[7:0] PRDATA[7:0] 00 ACMADDR[7:0] 02 04 00 ACMDATA[7:0] ACMCtrlStat ACMAddr ACMCtrlStat ACMData Note: 8-bit APB reads and writes are shown. Figure 6 * ACM Read Procedure 20 v2.0 CoreAI RTC Operation For detailed data on the connection and operation of the 40-bit real-time counter block within the AB macro, refer to the Fusion datasheet. The SmartGen software can be used to configure the RTC. The internal registers of the RTC are accessed via the Table 33 * RTC Control/Status Register Bits 7 6 Name rtc_rst cntr_en ACM interface address map listed in Table 32 on page 18. Control of the RTC is primarily accomplished via writes to the RTC CTRL_STAT (Control/Status) register at ACM address 0x58 (88), which is listed in Table 33. Status information is primarily obtained by reading the same register. Function RTC Reset: Writing logic 1 to this bit causes an RTC reset.1 Writing logic 0 to this bit will allow synchronous removal of reset after two ACM_CLK cycles if VCC33UP = 1.2 Counter Enable: Writing logic 1 to this bit will enable the counter if the RTC is not in reset. After reset is removed and cntr_en = 1, 64 RTCCLK positive edges (one-half of the pre-scaler division factor) will elapse before the counter is incremented.3 A logic 0 in this bit resets the pre-scaler and therefore suspends incrementing the counter, but the counter is not reset. Before writing to the COUNTER registers, the counter must be disabled. Voltage Regulator Enable on Match: Writing logic 1 to this bit will allow the RTCMATCH output port to transition to logic 1 when a match occurs between the 40-bit counter and the 40-bit match register. Logic 0 forces RTCMATCH to logic 0 to prevent enabling the voltage regulator from the RTC. Crystal Oscillator Mode: These bits control the RTCXTLMODE[1:0] output ports that are connected to the RTCMODE[1:0] input pins of the crystal oscillator pad. For 32 kHz crystal operation, this should be set to "01". Reset Counter on Match: Writing logic 1 to this bit allows the counter to clear itself when a match occurs. In this situation, the 40-bit counter clears on the next rising edge of the pre-scaled clock, approximately 4 ms after the match occurs (the pre-scaled clock toggles at a rate of 256 Hz, given a 32.768 kHz external crystal). Writing logic 0 to this bit allows the counter to increment indefinitely while still allowing match events to occur. Counter Reset: Writing logic 0 to this bit resets the 40-bit counter value to 0. Writing logic 1 allows the counter to count. Crystal Oscillator Enable: This bit controls the RTCXTLSEL output port that is connected to the SELMODE input pin of the crystal oscillator. If a logic 0 is written to this bit, only the FPGA fabric can be used to control the crystal oscillator EN and MODE[1:0] inputs. If a logic 1 is written to this bit, only the RTC can be used to control the RTCXTLSEL and RTCMODE[1:0] inputs of the crystal oscillator. This bit must be set to 1 to allow the RTC counter to function if the 1.5 V supply is off. 5 vr_en_mat 4:3 xt_mode[1:0] 2 rst_cnt_omat 1 0 rstb_cnt xtal_en Notes: 1. Reset of all RTC states (except this Control/Status register) occurs asynchronously if VCC33UP = 0 or CTRL_STAT bit 7 (rtc_rst) is written to 1. 2. Reset is removed synchronously after 2 rising edges of the ACM_CLK, following both VCC33UP = 1 and rtc_rst = 0. 3. Counter will first increment on the 64th rising edge of RTCCLK after all of the following are true: reset is removed, the rstb_cnt bit is set to 1, and the cntr_en bit is set to 1; it will then increment every 128 RTCCLK cycles. v2.0 21 CoreAI ADC Operation Control of the ADC within the AB macro in CoreAI is accomplished by APB reads and writes. After a power-up reset condition, the ADC will come out of its reset state and commence with its internal calibration sequence. When this calibration sequence has finished, the ADC will be ready to use for conversions. Read the INT[1:0] register bits to obtain status information relevant to the ADC calibration. The user must configure the analog quads appropriately via the ACM interface to match the required design-specific voltage, current, and temperature ranges prior to performing ADC conversions; failure to do so may result in damage to the Fusion device. The SmartGen software can be used to configure the analog quads and RTC. (internal or external), mode selection resolution), and clock divider settings. (ADC 3. Write the desired ADC settings to ADC Control register 2, including the sample time control and channel number to sample (1 of 32). 4. Set the Start Conversion bit to begin the conversion process. 5. If a current or temperature monitor operation is used on a corresponding AC or AT input pin, a write must be done to set the corresponding current or temperature monitor strobe high in ADC Control register 3 or ADC Control register 4, respectively. Refer to the Fusion datasheet for details on external component connection requirements for current and temperature monitoring. 6. Keep reading the high-order ADC Status register until the ADC is not busy performing a conversion. 7. If a current or temperature monitor operation has completed using a corresponding AC or AT input pin, a write must be done to set the corresponding current or temperature monitor strobe low in ADC Control register 3 or ADC Control register 4, respectively. 8. Read the low-order ADC Status register to obtain the lower 8 bits of the resulting ADC conversion data (the upper 4 bits of conversion data have already been read from the high-order ADC Status register). ADC Conversion Starts ADC Control A typical analog-to-digital conversion is shown starting in Figure 7 and ending in Figure 8 on page 23. The steps for performing an ADC conversion are as follows: 1. Read the ADC Status register to ensure that the ADC is not busy calibrating or performing a conversion. 2. Write the desired ADC settings to ADC Control register 1, including the voltage reference selection PCLK PADDR[4:0] PWRITE PSEL PENABLE PWDATA[7:0] PRDATA[7:0] 00 00 01 08 11 60 ADCStat(hi) ADCCtrl1(lo) ADCCtrl1(hi) ADCCtrl2(lo) ADCCtrl2(hi) ADCStat(hi) Note: 8-bit APB reads and writes are shown. Figure 7 * ADC Start of Conversion 22 v2.0 CoreAI ADC Conversion Ends PCLK PADDR[4:0] PWRITE PSEL PENABLE PWDATA[7:0] PRDATA[7:0] 20 15 55 ADCStat(hi) ADCStat(lo) Note: 8-bit APB reads and writes are shown. Figure 8 * ADC End of Conversion ADC Result Read FIFO An optional read FIFO, capable of holding up to 256 analog-to-digital conversions, is instantiated in CoreAI when the USE_RDFIFO parameter/generic is set to 1. The controlling element that is connected to CoreAI (internal or external microprocessor or microcontroller, or custom FPGA logic) can read resulting ADC conversions from this FIFO when desired. Resulting ADC conversion data is always written into the FIFO 12 bits at once, regardless of the ADC resolution (8-, 10-, or 12-bit), and is MSBjustified so that the resulting values are always of the same order of magnitude. The steps for reading resulting ADC conversion data from the read FIFO are as follows: 1. Read the Read FIFO Status register to check if there is data in the FIFO (not empty). 2. If the APB_16BIT_DATA parameter/generic is set to 0 (8-bit mode), read the Read FIFO Data Output register twice in a row to retrieve the lower 8 bits then the upper 4 bits of ADC conversion data. If the APB_16BIT_DATA parameter/generic is set to 1 (16-bit mode), read the Read FIFO Data Output register once to retrieve all 12 bits of ADC conversion data. 3. Repeat steps 1 and 2 until the Read FIFO is empty. Note that although the ADC conversion results are stored as one 16-bit word, the four upper bits of this 16bit word are reserved for possible future use. Since there is no channel information associated with each ADC conversion word, it is up to the user to maintain temporal coherency between conversions and resulting data. Interrupt Logic Although polling operations have been described to control the ACM and ADC, wherein status registers are periodically read (polled), the INTERRUPT output may be connected to a microprocessor or microcontroller to indicate similar events (e.g., ACM reads and writes completing, ADC calibration events, read FIFO events, etc.). In this case, interrupt service routines may be written in software to determine what actions, if any, should be taken for each of the interrupt events. Any or all interrupt events can be disabled by writing logic 0 values to the INTEN[14:0] register bits to mask the effect of each of the interrupt sources; it is the responsibility of the microprocessor/microcontroller software developer to determine what should or should not be masked. v2.0 23 CoreAI Ordering Information Order CoreAI through your local Actel sales representative. Use the following naming convention when ordering: CoreAI-XX, where XX is listed in Table 34. Table 34 * Ordering Codes Traditional (FTP) Delivery EV SN AN SR AR UR UG M Evaluation version Single use netlist Multiple use netlist Single use RTL Multiple use RTL CoreConsole Delivery Evaluations included with CoreConsole OC OM RC RM Obfuscated RTL - 1 year license Obfuscated RTL - multiple use license RTL source - 1 year license RTL source - multiple use license Unrestricted technology (on request) Upgrade Maintenance Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. 24 v2.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 51700066-0/3.06 |
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